The invention relates generally to data processing systems, and more particularly to a method and apparatus for maintaining data coherency in processing systems that include shared memory structures.
As computing systems continue to evolve, multiple processing entities often reside within the same computing system. These multiple entities may share memory structures such that data can easily be utilized by the multiple processing entities and such that the costs associated with including memory in the system are reduced. In some processing systems, processors may include localized memory such as caches in which they store small portions of the data included in the shared memory structure for faster and more efficient access. In such systems, data coherency issues can arise when the processing entity updates data in the localized memory without immediately updating the corresponding data in the shared memory structure.
Processing systems that include multiple processing entities typically include core logic, or glue logic, that serves to interface multiple bus structures, processors, memories, and other portions of the system that must work together. In such systems, the core logic block may be responsible for maintaining data coherency within the processing system. This is true in the case where a Peripheral Component Interconnect (PCI) bus is used to couple input/output devices or other processing entities to the core logic. In such systems, when the core logic receives a read request corresponding to a shared memory structure from a device coupled to the PCI bus, the address included with the read request is provided to the memory in order to fetch the data corresponding to the address. The address is also provided to any processors that may store a more current or modified version of the data such that those processors may flush their cache structures so that the memory will store the most current version of the data. If the processing entities that are queried to determine if they store more current version do not store a more current version, the core logic must be informed that a more current version does not exist outside of the memory structure. This is problematic in that each memory request over the PCI bus will force an access to each of the processors that may store more current versions of the data. This burdens the interfaces between the processors and the core logic and may also increase the bandwidth usage on the interface between the processor and the memory. Both of these effects starve the processor of valuable memory bandwidth that it needs in order to perform its processing functions.
Similar problems arise when an Accelerated Graphics Port (AGP) bus is used to couple an input/output device or other processing entity to the core logic. In such systems, the processor that may store a more current version of data than what is present in memory is typically responsible for ensuring that data coherency is maintained when memory requests are received over the AGP bus. The overhead required to maintain this coherency may be significant, and, as such, may interfere with the capability of the processor to efficiently perform the processing functions that it is required to implement. As such, the data coherency concerns can affect the overall processing system performance.
Therefore, a need exists for a method and apparatus for maintaining data coherency within a processing system that includes shared memory where the data coherency maintenance requires reduced interface bandwidth usage and reduced attention by processors or other entities included within the system.